FPD’96 -- Fourth Canadian Workshop of Field-Programmable Devices May 13-14, 1996, Toronto, Canada Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density

Field-Programmable Gate Arrays are interesting, general-purpose computational devices because (1) they have high computational density and (2) they have finegrained control of their computationalresources since each gate is independently controlled. The earlier provides them with a potential 10 advantage in raw peak performance density versus modern microprocessors. The later can afford a 32 advantage on random bit-level computations. Nonetheless, typical FPGA usage seldom extracts this full density advantage. DPGAs are less computationally dense than FPGAs, but allow most applications to achieve greater, yielded computational density. The key to unraveling this potential paradox lies in distinguishing instruction density from active computing density. Since the storage space for a single instruction is inherently smaller than the computational element it controls, packing several instructionsper computationalunit increases the aggregate instruction capacity of the device without a significant reduction in computational density. The number of different instructions executed per computational task often limits the effective computational density. As a result, DPGAs can meet the throughput requirements of many computing tasks with 3-4 less area than conventional FPGAs. 1 Computational Area “How big is a computation?” The design goal for “general-purpose” computing devices is to develop a device which can: implement desired computational tasks perform the computation at the desired latency or throughput realize the implementation at minimal cost – usually silicon area As device designers we are concerned with the area which a computational element occupies and its latency or throughput. We know, for example, that a four input Lookup Table (4-LUT) occupies roughly 640K 2 (e.g. 0.16mm2 in a 1 CMOS processor ( = 0:5 )) [1] [9]. Thus, we get a 4-LUT density of 1.6 4-LUTs per one million 2 of area. At the same time, we notice that the descriptive density of 4-LUT designs can be much greater than the 4-LUT density just observed. That is, the LUT configuration is small compared to the network area so that an idle LUT can occupy much less space than an active one. For illustrative purposes, let us assume that it takes 200 bits to describe the configuration for one 4-LUT, which is typical of commercial FPGA devices. A 64Mb DRAM would hold 335K such configurations. Since a typical 64Mb DRAM is 6G 2, we can pack 56 4-LUT descriptions per one million 2 of area – or about 35 the density which we can pack 4-LUTs. In fact, there is good reason to believe that we can use much less than 200 bits to describe each 4-LUT computation [3], making even greater densities achievable in practice. Returning to our original question, we see that there are two components which combine to define the requisite area for our general-purpose device: 1. Nd – the total number of 4-LUTs in the design – the descriptive complexity 2. Na – the total number of 4-LUTs which must be evaluated simultaneously in order to achieve the desired task time or computational throughput – the parallelism required to achieve the temporal requirements In an ideal packing, a computation requiring Na active FPD’96 -Fourth Canadian Workshop of Field-Programmable Devices May 13-14, 1996, Toronto, Canada K−LUT Memory Context ID D ec od e Context ID